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Figure 2 from Modeling and analysis of the dead-time effects in parallel two-level voltage source inverters | Semantic Scholar
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Figure 4 from Effects and Compensation of Dead-Time and Minimum Pulse-Width Limitations in Two-Level PWM Voltage Source Inverters | Semantic Scholar
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Figure 1 from Dead-Time Elimination of PWM-Controlled Inverter/Converter Without Separate Power Sources for Current Polarity Detection Circuit | Semantic Scholar
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Figure 4 from Dead-time compensation and realization method for 3-level NPC Inverter | Semantic Scholar
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